For those who may have missed it, Arduino recently launch a new board based on a FPGA ALTERA Cyclone 10LP. The MKR VIDOR 4000 is highly configurable and powerful, and it can perform high-speed digital audio like speech recognition for example and video processing.
What is on the board of the MKR vidor? Quick recap:
- 8 MB SRAM
- A 2 MB QSPI Flash chip — 1 MB allocated for user applications
- A Micro HDMI connector
- An MIPI camera connector
- Wi-Fi and BLE powered by a U-BLOX NINA W10 Series device
- MKR interface on which all pins are driven both by SAMD21 (32-bit ARM CPU) and FPGA
- Mini PCI Express connector with up to 25 user programmable pins
- The FPGA (an Intel/Altera Cyclone 10CL016) contains 16K Logic Elements, 504 KB of embedded RAM, and 56 18×18 bit HW multipliers
As you will notice, the documentation is still a bit sparse and not very available ye.
Our colleague from https://systemes-embarques.fr made a tutorial in french to how to reprogramm the user config of the FPGA. Since not many of you speak french, I did a translate of the first part:
Installation of Quartus
The FPGA is based on the ALTERA Cyclone 10LP, first you need to install le software Quartus:
- Go on the link of Altera and choose the last version of Quartus Lite Version
- The minimum you need are Quartus Prime (including Nios II EDS) and Cyclone 10 LP device support. Place then in a the same repertory.
- If you don’t have any Altera account you will probably have to create one.
Note : If you think you will use the USB Blaster case to program the FPGA you may need the package « Quartus II Programmer and SignalTap II » of the version Web Edition 13.0.
Once the download is completed, launch the .exe (QuartusLiteSetup-xx.yy-windows.exe).
If by default the installation gives you the choice, select the support for Cyclone 10LP in the following dialog box.
Basic Arduino Project.
Next step we need a base of project with the right configuration of I/O of the Arduino board. You can find it here.
Il nous faut ensuite avoir une base de projet avec les configurations d’E/S de la carte ARDUINO.
Vous pourrez trouver celle-ci à cet emplacement.
Unzip the ZIP file and open with Quartus (File → Open Project) the file MKRVIDOR4000.qpf.
You will find it int the tree structure: …\VidorFPGA-master\projects\MKRVIDOR4000_template
The top level module « Top level entity » is for this project the module: MKRVIDOR4000_top.
This file define:
- The name of I/O signals and their direction (input, output, inout,..),
- The internal links (Wire), buffers and registers (reg),…
- Instances of other modules ( ici cyclone10lp_oscillator et SYSTEM_PLL),
- Combinatorial rules (assign) or sequential (always/begin/end)
Another necessary file is the one that put in relation I/O signals with the prinning/routing of the FPGA. This file also define the volatge level of each signals so dont modify it!
You can see it with « Assignments → Assignments Editor ».
If you compile the project (Processing → Start compilation), and look at the generated architecture (Tools → Netlist viewers → RTL viewer), you will see that the project does not contain many things yet.
We are going to add a new sheet to the project:
Faites File→New et choisissez « Block Diagram/Schematic File »
A new window then opens. We can add and connect component like an electronic schematic. To blink a LED, what we need is an input port (a clock) and an output port (LED signal).
Add these ports (1 Input + 1 Output) in the sheet sur la feuille by clicking on the icone :
Then double click on the name, or right click and « Properties » : rename lthe input « iLEDCLK » and the output« oLED »:
Before adding any logic between these two ports, save the schematic (CTRL+S) with the name « TUTO_Schematic.bdf »
The clock that we will use in inout is the one provided by the internal oscillator of Cyclone 10 (around 80Mhz). This is too high, for our use. Instead of using a PLL with frequency we will use a counter.
With each clock strike in input, the count will increment. Every bit of the counter will change of state with its own frequency :
Freq_bit_n = ( Freq_entrée / (2 ^ (n+1)))
For a 1s blinking we will use n=25.
Adding the counter.
To add the counter, push the button « Symbol Tool » :
Select LPM_COUNTERand click on « OK » to put it in the schematic.
Then edit the counter’s properties (right click + « Properties ») enter the value 26 for LPM_WIDTH.
Then you will
– connect the input iLEDCLK to the clock of the counter usingthe command « Node Tool ».
– Take out a bus from the output q of the counter with the command «Bus Tool »
– Rename this bus « compteur[25..0] » (Right clickon the bus and « Properties »)
Finnaly, conenct with the tool Node Tool the output oLED to the bus compteur.
As we need only one of the signals of the bus, you need to tellQuartus which one (in our case : compteur)
You are done with schematic, save it RIGHT NOW!
The next step is to include the schematic in the «Top level entity » of the project.
To do this, double click on the file MKRVIDOR4000_top.v
And add the following lines: (above reg [5:0] rRESETCNT;) :
.iLEDCLK(wOSC_CLK) , // The input of the clock is connected to the intern osc 80MHz
.oLED(bMKR_D) // The outout of the LED is connected to the pin 6 of the port MKR
All you have to do is recompile the project:
Create the files app.h.
The compilation generated a file MKRVIDOR4000.ttf in the folder output_files. This file list in text format the byte of the FPGA configuration. We need to invert bit by bit every byte before send it to the ARDUINO board. To do this, download the software here.
Execute the command: java ReverseByte MKRVIDOR4000.ttf app.h
It will generate the file app.h that you can include into your empty sketch available here.
All you need now is to load the sketch in the board using the arduino IDE.
– In no case you should reconfigure the port PA20 du SAMD21in output.
– The port PA20 (nommé bMKR_D coté FPGA) corresponding to the pin 1 of the connector J5 (marked « 6 »). You have to connect a LED in serie with a resistor between this pin and the ground to see te LED blinking.